1. Field of the invention
The present invention relates to a dynamic RAM (DRAM) cell, and more particularly to a method of making a DRAM cell which is capable of increasing storage capacity by parallel connecting a trench capacitor with a stack capacitor.
2. Description of the Prior Art
One DRAM cell comprises one transistor in which a drain-source channel is coupled between a bit line and a cell node, and one storage capacitor which is connected between the cell node and cell plate. By the increase of DRAM memory density, there has been developed a DRAM cell having a trench capacitor and stack structure in order to maximize storage capacity on a fixed area occupied by DRAM cell.
FIG. 1 is a cross-sectional view showing a preferred embodiment of a known trench capacitor cell.
As shown in FIG. 1, a known trench capacitor cell comprises a N-channel MOS transistor, a diffusion layer 8, a dielectric film 9 and a polycrystalline silicon 11. The N-channel MOS transistor comprises a source region 3 which is adjacent to a field oxide 10 formed on the surface of a p-type substrate 1, a drain region 2 separated through channel, and a word line 5 formed by a polycrystalline silicon of a conductivity type being grown on a gate oxide 4 on the substrate between the drain 2 and source region 3. The diffusion layer 8 is formed on the outside substrate of a trench 7, and utilized as a cell node by contacting with the source region 3. The dielectric film 9 is formed on the inside of trench 7. The polycrystalline silicon 11 on the dielectric film 9 is used as a cell plate by filling up the trench. Also, adjacent word line 6, being a gate electrode of adjacent memory cell, is formed on a portion of field oxide 10 with being separated from the polycrystalline silicon layer 11 by an insulating film 12.
In the trench capacitor described above, a trench must be deeply dug in order to have a large storage capacity, so a transistor is formed after forming the capacitor, a diffusion layer formed under trench is extended by continuous process steps. If large scale integration of DRAM memory cell causes the distance between trenches and to decrease the distance of diffusion regions of adjacent cells to be very narrow, so that there is a problem that information stored in the capacitor is lost due to leakage current flowing through a substrate.
FIG. 2 is a cross-sectional view showing a preferred embodiment of a known stack capacitor.
As shown in FIG. 2, a known stack capacitor includes a N-channel MOS transistor, a dielectric film 29 and a polycrystalline silicon layer 31. The N-channel MOS transistor has a source region 22 which is adjacent to a field oxide layer 30 formed over the p-type semiconductor substrate 20, a drain region 21 separated by a channel, and a word line 24 formed by a polycrystalline silicon of a conductivity type being grown over a gate oxide layer 23 on the substrate between the drain 21 and source region 22. The dielectric film 29 used of dielectric material is formed on the inside surface of a trench 26 which is formed in the substrate under the source region 22. The polycrystalline silicon 31 formed over the dielectric film 29 is used as a cell plate layer. Also, word lines 24, 25 and a polycrystalline silicon layer 27 used as a cell node layer, are separated by an insulating film 28, and a bit line 35 separated by an insulating film 34 over polycrystalline silicon layer 31 utilized as a cell plate layer, is connected with drain region 21 through an opening hole. The insulation film 34 consists of oxide film 32 and BPSG film (Boro-phospho Silicate Glass) 33.
However a stack capacitor described above has a small rate of increase in storage capacity according to extension of area by trench process due to a fixed thickness of a polycrystalline silicon layer used for the cell node layer, there is also a problem that if a trench hole is small, it is difficult to deposit a polycrystalline silicon layer for forming a cell plate over the inside trench.